High-speed communication links (e.g., ˜5 Gb/s and higher per differential pair) typically include backplanes right angle connectors and or mother-board daughter-board configurations with stacking connectors. Plated through hole (PTH) connector pinfields of such right-angle and stacking connectors, whether press-fit or surface-mount, are one of the major causes of problems in printed circuit boards (PCB) that provide the routing for such connectors. In particular, the constrained routing of the pinfield geometry results in an undesirable situation wherein the impedance of signal vias is less than the 50 ohms single-ended (and less than 100 ohms differential), the impedance achieved by the rest of the communication channel, degrading performance.
In FIG. 1, one layer of a conventional multistack PCB 10 is depicted having a reference (ground) plane (e.g., copper plated on a substrate) 12 that is understood to overlay a substrate (note shown). The reference plane 12 overlies an orthogonal rectangular array of ground via pads 14 that surround respective ground via drill holes 18, forming a reference via 20; the ground via drill holes 18 may have inserted ground pins 16 in case of press-fit connectors or they may be hollow in case of surface mount connectors Another orthogonal rectangular array exists of signal via drill holes 24, each respectively centered among four adjacent grounding vias 18. Signal via drill holes may have inserted signal pins 22 in case of press-fit connectors or they may be hollow in case of surface mount connectors. Surrounding each signal via drill hole 24, a signal via pad 28, contacting conditionally the respective inserted signal pin 22, forms a signal via 30 for possible connection to a one of a plurality of traces 32. The metal of the reference plane 12 is removed for replacement by a circular anti-pad 34 of dielectric insulating material forming an annular ring surrounding each signal via 30.
The traces 32 are arranged as signal straddling differential pairs, for instance depicted as a first differential pair 36a composed of a lower trace 38a and an upper trace 40a and an adjacent second differential pair 36b composed of a lower trace 38b and upper trace 40b. Each pair 36a, 36b approaches a respective horizontal row of signal vias 30 from slightly below and slightly above centerline, respectively, and spreading apart to clear opposite sides of each anti-pad 34 for the respective row of anti-pads 34 until a particular signal via 30 is reached for each trace 38a, 38b, 40a, 40b, or until the differential pair clears through the pinfield.
The impedance of a typical signal via of a component pinfield in a typical multilayered PCB 10 with FR4 dielectric is always less than 50 ohms. The impedance depends largely on the diameter of the signal via drill hole 24, the diameter of the anti-pads 34, the dielectric constant of the insulating material, diameter and locations of the signal via pads 28, and spacing of the signal via drill holes 24 and ground via drill holes 18. It is desirable that the impedance be as close to 50 ohms as possible, which would be feasible if sufficient increase in diameter were available for the anti-pads 34. However, too large of a size would result in an also undesirable routing of traces overtop of the anti-pads 34 or reducing the separation between adjacent pairs 30a, 30b, resulting in increased cross talk between differential pairs 30a, 30b. 